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? semiconductor components industries, llc, 2012 september, 2012 ? rev. 0 1 publication order number: br262/d belasigna r262 wideband voice capture and noise reduction solution introduction belasigna ? r262 is a complete system ? on ? chip (soc) solution that provides wideband advanced noise reduction in voice capture applications such as mobile phones, voip applications such as webcams and tablet computers, two ? way radios and other applications that will benefit from improved voice clarity. featuring a novel approach to removing mechanical, stationary and non ? stationary noise, the chip preserves voice naturalness for greater voice clarity and speech intelligibility even when the talker is further away or not optimally aligned with the microphones providing unmatched freedom of movement for end ? users. designed to be compatible with a wide range of codecs, baseband chips and microphones without the need for calibration, belasigna r262 is easy to integrate, improving manufacturers? speed to market. additional features include the ability to provide two simultaneously processed outputs and to configure them depending on the needs of a manufacturer?s device. the chip includes a highly optimized dsp ? based application controller with industry ? leading energy efficiency and is packaged in two highly compact 5.3 mm 2 wlcsps to fit into even the most sized ? constrained architectures and allows the use of common industry printed circuit board design technologies. key features and benefits ? drop ? in solution that works without special tuning ? consistently captures voice regardless of acoustic environment or the orientation of the handheld device while in use ? 360 voice pick ? up adjustable from 5 cm to 5 m ? no constraints on industrial design or microphone model ? simultaneous dual ? configurable outputs ? de ? reverberation ? low power consumption (17 ma active and 40 a stand ? by) ? miniature size allows easy integration into existing industrial designs typical applications ? mobile phones ? notebook and tablet computers ? two ? way radios and ptt devices ? voip applications ? any device that would benefit from improved voice pick ? up http://onsemi.com br262 w30 alyw 1 marking diagrams wlcsp ? 30 w suffix case 567ct see detailed ordering and shipping information in the package dimensions section on page 28 of this data sheet. ordering information br262 = belasigna r262 w30 = 30 ? ball version w26 = 26 ? ball version a = assembly location l = wafer lot yw = date code year & week = pb ? free package = a1 corner indicator wlcsp ? 26 w suffix case 567cy br262 w26 alyw 1 orientation br262 w30 alyw 1
belasigna r262 http://onsemi.com 2 table 1. absolute maximum ratings parameter min max unit power supply (applies on vbat, vbatrcvr and vddo for ?max? and for vssa, vssrcvr and vssd for ?min?) (note 1) ? 0.3 4.0 v digital input pin voltage vssd ? 0.3 v vddo + 0.3 v v operating temperature range ? 40 85 c storage temperature range ? 40 85 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. time limit at maximum voltage must be less than 100 ms. note: refer to electrical characteristics and application information for safe operating area. this device series incorporates esd protection and is tested by the following methods: ? esd human body model (hbm) tested per aec ? q100 ? 002 (eia/jesd22 ? a114) ? esd machine model (mm) tested per aec ? q100 ? 003 (eia/jesd22 ? a115) this device series incorporates latch ? up immunity and is tested in accordance with jesd78. electrical performance specifications table 2. electrical characteristics (the typical parameters in table 2 were measured at 20 c with a clean 3.3 v supply voltage (unless noted differently). parameters marked as screened are tested on each chip. other parameters are qua lified for all process corners but not tested on every part.) parameter symbol test conditions / notes min typ max unit screened overall supply voltage vbat 1.65 3.3 3.63 v maximum rise time between 0 v and 1.8 v 10 ms average current consumption active mode, vbat = 3.3 v, ext_clk = 2.048 mhz 16.0 16.5 17.0 ma bypass mode, vbat = 3.3 v, ext_clk = 2.048 mhz 16.0 16.5 17.0 ma bypass mode, vbat = 3.3 v, internal clock 2.7 2.8 2.9 ma sleep mode, vbat = 3.3 v 39 40 a peak active current vbat = 3.63 v 19 21 ma vreg (1 f external capacitor) output voltage vreg without load, or with micro- phone attached (0 to 200 a) 0.95 1.00 1.05 v psrr @ 1 khz 40 db load regulation @ 2 ma 5 20 mv/ma load current 2 ma line regulation ? 1 5 mv/v vdda (1 f external capacitor on vdda + 100 nf external capacitor on cap0/cap1) output voltage vdda unloaded with vreg = 1 v 1.8 2.0 2.1 v psrr @ 1 khz 45 db load regulation @ 1 ma 100 140 mv/ma load current 1 ma line regulation 2 mv/v vddd (1 f external capacitor) output voltage vddd 1.62 1.70 1.98 v
belasigna r262 http://onsemi.com 3 table 2. electrical characteristics (continued) (the typical parameters in table 2 were measured at 20 c with a clean 3.3 v supply voltage (unless noted differently). parameters marked as screened are tested on each chip. other parameters are qua lified for all process corners but not tested on every part.) parameter screened unit max typ min test conditions / notes symbol vmic output voltage vmic = vreg 0.95 1.00 1.05 v vmic = vdda 1.8 2.0 2.1 v load regulation vmic = vreg 25 40 mv/ma vmic = vdda 100 150 mv/ma power on reset por threshold por release (vbat going up) 1.52 1.60 1.71 v por activation (vbat going down) 1.52 1.60 1.65 v boot time nrst to dmic active using lsad boot method 16.3 ms nrst to dmic active using spi eeprom boot method (default custom application) 90 ms nrst to dmic active using i2c eeprom boot method (default custom application) 135 ms input stage sampling frequency fs defined by rom ? based application. (note 2) 21.333 khz analog input voltage vin no preamp gain on ai1 and ai3 0 2 vpp vin 24 db preamp gain by default on mic0 and mic2 0 125 mvpp preamplifier gain tolerance 1 khz ? 2 2 db input impedance rin 0 db preamplifier gain 250 k all other gain settings 510 585 k input offset voltage 0 db preamp gain 7 mv all other gains 3 mv channel cross coupling any 2 channels ? 84 ? 60 db analog filter cut ? off frequency lpf enabled (default) 10 20 30 khz lpf disabled 50 khz analog filter passband flatness ? 1 1 db analog filter stopband attenuation 60 db digital filter cut ? off frequency fs/2 khz digital filter cut ? off stopband attenuation 80 db total harmonic distortion + noise (peak value) thdn 24 db preamplifier gain vbat = 3.3 v ? 67 ? 70 db dynamic range dr 24 db preamplifier gain vbat = 3.3 v 81 82.5 db equivalent input noise ein 24 db preamplifier gain vbat = 3.3 v 3.7 v 2. processed bandwidth limited to 8 khz.
belasigna r262 http://onsemi.com 4 table 2. electrical characteristics (the typical parameters in table 2 were measured at 20 c with a clean 3.3 v supply voltage (unless noted differently). parameters marked as screened are tested on each chip. other parameters are qua lified for all process corners but not tested on every part.) parameter symbol test conditions / notes min typ max unit screened digital microphone output dmic input clock frequency with preset 0 selected on clock_sel (note 3) 2.048 mhz with preset 3 selected on clock_sel (note 3) 2.4 mhz with preset 4 selected on clock_sel (note 3) 2.8 mhz with preset 5 selected on clock_sel (note 3) 3.072 mhz clock duty cycle any clock configuration 40 50 60 % input clock jitter maximum allowed jitter on the dmic_clk 10 ns clock to output transition time dmic_out 10 20 50 ns analog output stage signal range vout one single ended dac used 0 2 vpp two dacs used as one differential output 0 4 vpp attenuator gain tolerance ? 2 2 db output impedance rout @ 12 db output attenuation 19 k @ 0 db output attenuation 3 k channel cross coupling @ 1 khz ? 50 db analog filter cut ? off frequency lpf enabled (default) 13.0 13.5 khz lpf disabled 25 26 khz analog filter passband flatness ? 1 1 db analog filter stopband attenuation > 60 khz 90 db digital filter cut ? off frequency fs/2 khz digital filter cut ? off stopband attenuation 80 db total harmonic distortion + noise (peak value) thdn 63 65 db dynamic range dr 78 80 db noise floor 70 100 v direct digital output (available only through custom configuration) supply voltage vbatrcvr 1.8 3.3 3.63 v signal range vout differential output @ 1 khz 0 2*vbat rcvr vpp single ended output @ 1 khz 0 vbat rcvr vpp output impedance rout load between 1 ma and 30 ma @ 0 c 2.5 10 maximum current 25 ma total harmonic distortion + noise (peak value) thdn 64 70 db 3. many other clock frequencies are available through custom configuration of the internal pll and clocking subsystem. see later in this document and in the belasigna r262 communications and configuration guide for more information on custom mode usage.
belasigna r262 http://onsemi.com 5 table 2. electrical characteristics (continued) (the typical parameters in table 2 were measured at 20 c with a clean 3.3 v supply voltage (unless noted differently). parameters marked as screened are tested on each chip. other parameters are qua lified for all process corners but not tested on every part.) parameter screened unit max typ min test conditions / notes symbol direct digital output (available only through custom configuration) dynamic range dr 80 86 db noise floor 50 75 v low ? speed a/d input voltage vin 0 2*vreg v sampling frequency for each lsad channel 1.6 mclk/28 4.8 khz input impedance rin 1 m offset error input at vreg ? 10 10 lsb gain error input to vssa or 2*vreg ? 10 10 lsb inl inl ? 4 4 lsb dnl dnl ? 2 2 lsb digital pads (vddo = 1.8 v) voltage level for low input vil ? 0.3 0.4 v voltage level for high input vih 1.30 1.98 v pull ? up resistance 63 114 162 k pull ? down resistance 87 153 205 k rise and fall time 20 pf load 2 3 5 ns digital pads (vddo = 3.3 v) voltage level for low input vil ? 0.3 0.8 v voltage level for high input vih 1.8 3.6 v pull ? up resistance 34 46 74 k pull ? down resistance 29 56 86 k rise and fall time 20 pf load 1.0 1.5 2.0 ns digital pads (common parameters) drive strength 12 ma esd immunity hbm human body model 2 kv mm machine model 200 v latch ? up immunity 25 c, v < gndo, v > vddo 150 ma clocking circuitry external clock frequency ext_clk with preset 6 selected on clock_sel (note 3) 26 mhz internal clock frequency int_clk with preset 7 selected on clock_sel (note 3) bypass mode 5.2 mhz with preset 7 selected on clock_sel (note 3) active mode 48.2 mhz reference clock duty cycle 40 50 60 % external input clock jitter maximum allowed jitter on ext_clk 10 ns i 2 c interface maximum speed 400 kbps 3. many other clock frequencies are available through custom configuration of the internal pll and clocking subsystem. see later in this document and in the belasigna r262 communications and configuration guide for more information on custom mode usage.
belasigna r262 http://onsemi.com 6 table 3. pin connections pin index pin name description a/d/p i/o active pull g1 mic0 first microphone input a i e5* ai1/lout1 direct audio input / line ? out preamp 1 a i/o e1 mic2 second microphone input a i e3 ai3/vmic/lout0 direct audio input / microphone bias / line ? out preamp 0 a i/o d6* a_out0 audio output 0 a o e7 a_out1 audio output 1 a o g7 cap0 charge pump capacitor connection a i/o f8 cap1 charge pump capacitor connection a i/o a1 debug_rx rs232 debug port serial input d i l u b2 debug_tx rs232 debug port serial output d o l f2 reserved reserved a3 ext_clk external clock input d i u a7 spi_clk/clock_sel spi clock / clock selection d/a o/i l/ ? a9 spi_cs/boot_sel spi chip select / booting method selection d/a o/i b8 spi_sero/chan_sel spi serial output / channel selection d/a o/i c9 spi_seri/alpha_sel spi serial input / mixing ratio selection d/a i/i u/ ? c7 dmic_out digital microphone output d o c5* swap_chan channel swap control d i u c3 i2c_sda i 2 c data d io l u c1 i2c_scl i 2 c clock d io l u d4* nreset reset d i l u f6 vbat power supply p i g9 vbatrcvr output driver power supply p i g5 vdda analog supply voltage p o b6 vddd digital power supply p o b4 vddo digital i/o power supply p i g3 vreg analog supply voltage p o f4 vssa analog ground p i a5 vssd digital ground p i e9 vssrcvr output driver ground p i * pins c5, d4, d6 and e5 are not available on the wlcsp26 package. all pins are available on the wlcsp30 package. a: analog pin d: digital pin p: power pin i: input o: output io: bi ? directional i/o & o/il: input or output depending on the function being used l: active low h: active high u: pulled up internally d: pulled down internally
belasigna r262 http://onsemi.com 7 application diagrams figure 1. typical application diagram for 30 ? ball wlcsp package option mux belasigna r262 a/d a/d mic0 mic2 vmic microphone 0 microphone 2 a_out0 laptop codec or baseband chip ext_clk vssrcvr vssa + ? vbat vssd vbatrcvr cap0 cap1 vddd vssd 1uf 1uf 10nf 100nf vdda vssa 1uf 1.8v ? 3.3v vssd vddo advanced speech and noise management d/a d/a dmic dmic_out vreg vssa 1uf vssd 1uf chan_sel alpha_sel vreg agnd vreg agnd clock_sel boot_sel vreg vreg agnd agnd a_out1 2.2uf 2.2 k
belasigna r262 http://onsemi.com 8 applications information recommended circuit design guidelines belasigna r262 is designed to allow both digital and analog processing in a single system. due to the mixed ? signal na ture of this system, careful design consideration of the printed circuit board (pcb) layout is critical to maintain the high audio fidelity of belasigna r262. to avoid coupling noise into the audio signal path, keep the digital traces away from the analog traces. to avoid electrical feedback coupling, isolate the input traces from the output traces. recommended ground design strategy the ground plane should be partitioned into two parts: the analog ground plane (vssa) and the digital ground plane (vssd). these two planes should be connected together at a single point, known as the star point. the star point should be located close to the negative terminal of the power source, as illustrated in figure 2. all ground returns should be routed separately back to the appropriate ground plane, i.e. do not share a ground return. ensure that different ground and/or power planes do not overlap each other if located on different layers in the board. figure 2. schematic of ground scheme belasigna r262 vbatrcvr vddo vddd vdda vreg digital ground plane (keep away from analog ground plane, place under digital side of br262) vssd analog ground plane (place under analog side of br262) vssa + battery 1.8v ? 3.3v vssrcvr ground (route separately to star ground point) vssrcvr start ground point vbat
belasigna r262 http://onsemi.com 9 figure 3. proposed ground plane positioning (soldering footprint view) 123456789 analog ground plane g e f c d b digital ground plane a g1 g3 g5 g7 g9 f2 f4 f6 f8 d4 d6 e1 e3 e5 e7 e9 a1 a3 a5 a7 a9 b2 b4 b6 b8 c1 c3 c5 c7 c9 f6 = vbat d6 = a_out0 e7 = a_out1 g7 = cap0 f8 = cap1 g9 = vbatrcvr e9 = vssrcvr b6 = vddd c7 = dmic_out a7 = spi_clk a7 = clock_sel b8 = spi_sero b8 = chan_sel a9 = spi_cs a9 = boot_sel c9 = spi_seri c9 = alpha_sel f2 = reserved g3 = vreg e3 = vmic g1 = mic0 e1 = mic2 f4 = vssa d4 = nreset g5 = vdda e5 = ai1 c1 = i2c_scl c3 = i2c_sda c5 = swap_chan b4 = vddo a5 = vssd a3 = ext_clk a1 = debug_rx b2 = debug_tx the vssd plane is used as the ground return for digital circuits and should be placed under digital circuits. the vssa plane should be kept as noise ? free as possible. it is used as the ground return for analog circuits and it should surround analog components and pins. it should not be connected to or placed under any noisy circuits such as rf chips, switching supplies or digital pads of belasigna r262 itself. analog ground returns associated with the audio output stage should connect back to the star point on separate individual traces. for details on which signals require special design consideration, see table 4 and table 5. in some designs, space constraints may make separate ground planes impractical. in this case a star configuration strategy should be used. each analog ground return should connect to the star point with separate traces. internal power supplies power management circuitry in belasigna r262 generates separate digital (vddd) and analog (vreg, vdda) regulated supplies. each supply requires an external decoupling capacitor, even if the supply is not used externally. decoupling capacitors should be placed as close as possible to the power pads. the digital i/o levels are defined by a separate power supply pin on belasigna r262 (vddo). this pin must be externally connected by the application pcb, usually to vbat. further details on these critical signals are provided in table 4. non ? critical signals are outlined in table 5. more information on the power supply architecture can be found in the power supply unit section.
belasigna r262 http://onsemi.com 10 table 4. critical signals pin name description connection guidelines vbat power supply place 1 f (min) decoupling capacitor close to pin connect negative terminal of capacitor to digital ground plane vreg, vdda internal regulator for analog blocks place separate 1 f decoupling capacitors close to each pin connect negative capacitor terminal to analog ground plane keep away from digital traces and output traces vreg and vdda may be used to generate microphone bias vssa analog ground return connect to analog ground plane vddd internal regulator for digital core place 1 f decoupling capacitor close to pin connect negative terminal of capacitor to digital ground plane vssd digital ground return connect to digital ground plane vddo digital i/o power place 1 f decoupling capacitor close to pin connect negative terminal of capacitor to digital ground plane connect to vbat, unless the pad ring must use different voltage levels mic0, mic2, ai1/lout1, ai3/vmic/lout0 audio inputs / microphone bias keep traces as short as possible keep away from all digital traces and audio outputs avoid routing in parallel with other traces never connect ai3/vmic/lout0 to ground a_out0, a_out1 audio outputs keep away from audio inputs differential traces should be of approximately the same length ideally, route lines parallel to each other vssrcvr output stage ground return connect to star ground point keep away from all analog audio inputs ext_clk external clock input minimize trace length keep away from analog signals if possible, surround with digital ground dmic_out digital microphone output minimize trace length keep away from analog signals if possible, surround with digital ground
belasigna r262 http://onsemi.com 11 table 5. non ? critical signals pin name description connection guidelines cap0, cap1 internal charge pump ? capacitor connection place 100 nf capacitor very close to pins i2c_sda, i2c_scl i 2 c port keep as short as possible. place pull ? up resistors (10 k ) to vddo swap_chan control gpio not critical when used as gpio clock_sel, boot_sel, chan_sel and alpha_sel low ? speed a/d converters (multiplexed with spi port) not critical when used as lsad place resistive divider for hardware configuration of belasigna r262 spi_clk, spi_cs, spi_sero, spi_seri serial peripheral interface port (multiplexed with lsad and gpios) keep away from analog input lines when used as spi signals nreset reset not critical leave unconnected if unused debug_rx, debug_tx debug port not critical if possible, connect to test points, otherwise connect debug_rx to vddo and leave debug_tx floating reserved reserved pin leave unconnected or connect to vssa if pcb routing constraints force it vbatrcvr output driver power supply if the output driver is being used: ? place a separate 4.7 f (min. 2.2 f) decoupling capacitor close to pin ? connect positive terminal of capacitor to vbat & vbatrcvr ? connect negative terminal of capacitor to vssrcvr if the analog outputs or the dmic output are being used: ? separate decoupling capacitor on vbatrcvr is not required ? connect vbatrcvr to vdda (which has its own decoupling capacitor) audio inputs the audio input traces should be as short as possible. the input impedance of each audio input pad (e.g., mic0, ai1, mic2, ai3) is high (approximately 500 k with preamplifiers enabled); therefore a 10 nf capacitor is sufficient to decouple the dc bias. this capacitor and the internal resistance form a first ? order analog high pass filter whose cut ? off frequency can be calculated by f 3db (hz) = 1/(r x c x 2 ), which results in ~30 hz for a 10 nf capacitor. this 10 nf capacitor value applies when the preamplifier is being used, in other words, when a non ? unity gain is applied to the signals; for mic0 and mic2, the preamplifier is enabled by the rom ? based application. when the preamplifier is bypassed, the impedance is reduced; hence, the cut ? off frequency of the resulting high ? pass filter could be too high. in such a case, the use of a 30 ? 40 nf serial capacitor is recommended. in cases where line ? level analog inputs without dc bias are used, the capacitor may be omitted for transparent bass response. on semiconductor recommends the use of npo/cog dielectric for smt capacitors, as they have demonstrated better performance compared to other capacitors with x7r dielectric. microphone power supply belasigna r262 provides a microphone power supply (vmic) and ground (vssa). in case vmic cannot be used because of pcb routing constraints, the power supplies vreg (1.0 v) or vdda (2.0 v) can alternatively be used. keep audio input traces strictly away from output traces. audio outputs must be kept away from microphone inputs to avoid cross ? coupling. audio outputs the audio output traces should be as short as possible. the trace length of the two signals should be approximately the same to provide matched impedances. recommendation for unused pins table 6 shows the connection details for each pin when they are not used. table 6. unused pin recommendations signal name connection guidelines a_out0 do not connect a_out1 do not connect ai3/vmic/lout0 do not connect ai1/lout1 connect to vssa dmic_out do not connect swap_chan do not connect nreset do not connect
belasigna r262 http://onsemi.com 12 architecture detailed information the architecture of belasigna r262 is shown in figure 4. figure 4. belasigna r262 architecture: a complete audio processing system pll and clock detection mux spi uart gpio belasigna r262 preamps decimation a/d a/d pcm/i2s custom mode handler dsp ? based application controller advanced speech and noise management algorithm control sleep mode control h/w config selection boot selection command handler interpolation d/a d/a dmic debug port power mgt lsad mode switching i 2 c system monitoring i 2 c
belasigna r262 http://onsemi.com 13 advanced speech and noise management system belasigna r262 contains an advanced noise reduction algorithm inside its rom memory which preserves voice quality while significantly reducing background noise. the algorithm identifies and enhances human speech. many two ? microphone algorithms depend on beamforming and rely on the speech originating from a specific direction. as a result, the performance of these algorithms can vary greatly depending on the location of the speech and the noise relative to the microphones, and typically will distort the speech as well as the noise. other algorithms that depend on a speech ? facing microphone and a noise ? facing microphone can require a lot of algorithm tuning for reasonable performance. belasigna r262 is different as it is a true 360 self ? adaptive multi ? beamformer that distorts neither speech nor noise. it applies attenuation or gain based on intelligent classification of signals, resulting in a signal where the noise is attenuated, and the speech is enhanced. the attenuated noise is left as natural as possible so other downstream processing is still effective. at the same time it performs de ? reverberation of the received signals. the solution is ideal for any voice capture device requiring consistent performance in noisy environments. unlike other purely directional solutions, belasigna r262 will not drop your voice when you change orientation of the handheld device. the algorithm works with two forward ? facing microphones spaced 10 to 30 mm apart (typically), and no tuning or matching of microphones is required. the speech source can come from any direction (normally in front of the microphones), as long as it is within the working sphere of the current algorithm mode. the algorithm mode is set based on the required talking distance (distance between the mouth reference point and the microphones), with noise reduction performance decreasing as talk distance increases. belasigna r262 can be set to perform maximum noise reduction with a talk distance of 5 to 10 cm, mild noise reduction with improved voice pickup at up to 5 m away, or anywhere in between. the noise reduction algorithm built into belasigna r262 can provide two processed outputs, each with different tuning or operating parameters, which can serve two different use cases simultaneously. an unlimited number of use cases can be obtained by configuring belasigna r262, where the user can easily select the appropriate distance between the device?s microphones and the user?s mouth. any two of these use cases can be selected to the output stage, allowing the target application to simultaneously support use cases with mouth ? to ? microphone distances varying between 5 cm and 5 m. for additional details on the configuration of the algorithm, please refer to belasigna r262 communications and configuration guide. algorithm performance belasigna r262 offers three main algorithm modes; the close ? talk mode aggressively filters noise and manages gain to pick up speech within 5 to 10 cm from the microphone array. the algorithm is not sensitive to handset holding style in any mode, including close ? talk mode. the near ? talk mode can effectively pick up speech within 0.5 m to 1 m from the microphone array, an intermediate situation between far ? talk and close ? talk modes. this is suitable for capturing speech when using the device at arm?s length. the far ? talk mode detects and enhances speech from a distance, but removes less overall environmental noise compared to close ? talk mode. far ? talk mode is suitable for recording lectures or processing conference calls on speakerphone. in addition to these three main modes (close, near and far), belasigna r262 features a mixing capability, which allows the selection of any two of these three main modes combined through a mixing ratio to create any intermediate mode, allowing manufacturers to fine tune the algorithm based on the microphone ? to ? user distance on the target device. a selection of performance metrics are shown in table 7 for some input signal ? to ? noise ratios and noise types. signal ? to ? noise ratio improvement (snr ? i) was measured according to the itu ? t g.160 standard, with belasigna r262 operating on reference hardware, in conjunction with common omni ? directional microphones (ecms) positioned 11 mm away from each other. to verify that subjective quality was maintained through the noise management process, a perceptual enhancement of speech quality (pesq) measurement was also taken for each condition. pesq improvement correlates to mos improvement, the widely ? accepted subjective standard in voice quality.
belasigna r262 http://onsemi.com 14 table 7. algorithm performance parameter test conditions value unit close ? talk mode (5 cm to 10 cm talking distance) snr improvement (snr ? i) white noise, 6 db snr 30.0 db babble noise, 9 db snr 20.6 db pink noise, 12 db snr 19.9 db pesq improvement white noise, 6 db snr 0.8 ? babble noise, 9 db snr 0.3 ? pink noise, 12 db snr 0.4 ? near ? talk mode (50 cm to 100 cm talking distance) snr improvement (snr ? i) white noise, 6 db snr 19.6 db babble noise, 9 db snr 10.6 db pink noise, 12 db snr 14.5 db pesq improvement white noise, 6 db snr 0.5 ? babble noise, 9 db snr 0.4 ? pink noise, 12 db snr 0.4 ? far ? talk mode (2.5 m to 5 m talking distance) snr improvement (snr ? i) white noise, 6 db snr 14.7 db babble noise, 9 db snr 6.9 db pink noise, 12 db snr 11.1 db pesq improvement white noise, 6 db snr 0.7 ? babble noise, 9 db snr 0.4 ? pink noise, 12 db snr 0.5 ? pick ? up distance belasigna r262 is a fully adaptive system that will automatically adjust its signal processing algorithm depending on the input conditions. the three modes discussed in this document, close ? talk, near ? talk and far ? talk, all have distinct use cases. each of these modes will adjust the distance from the microphone that they ef fectively capture speech based on the amount of noise present. as an example, the close ? talk algorithm will allow a pick ? up distance up to 15 cm in very quiet situations, whereas it will shrink the pick ? up distance down to between 5 cm and 10 cm when the noise around the microphone increases. close ? talk mode is designed to handle high noise situations; up to 90 db spl. near ? talk mode is tuned to pick up speech within 50 cm to 100 cm in a quiet environment, and will shrink the pick ? up distance down 20 cm to 30 cm if the noise level increases. given the extended pick ? up distance, compared to close ? talk mode, voice is effectively captured in noise situations up to 70 db spl with extremely good noise reduction. far ? talk mode is designed to handle lower noise levels (up to 50 db spl) with a much larger pick ? up distance. figures 5, 6 and 7 below show the optimal talking distance for the three algorithm modes as a function of the input signal ? to ? noise ratio. when designing belasigna r262 into a device, it is important to assess the targeted use case of the product and to consequently select an appropriate algorithm mode. it is also important to realize that the three modes discussed here are just examples of what can be obtained with belasigna r262. adjustment of the talking distance and the noise reduction aggressiveness are just two of the performance parameters that can be controlled.
belasigna r262 http://onsemi.com 15 typical characteristics optimized talking distance (cm) figure 5. close ? talk figure 6. near ? talk input signal ? to ? noise ratio (db) input signal ? to ? noise ratio (db) 6 9 12 15 18 21 0 2 4 6 8 10 14 16 6 9 12 15 18 21 0 20 40 60 80 100 120 figure 7. far ? talk input signal ? to ? noise ratio (db) 6 9 12 15 18 21 0 100 200 300 400 500 600 700 optimized talking distance (cm) optimized talking distance (cm) 12
belasigna r262 http://onsemi.com 16 microphone placement & selection the flexibility of the belasigna r262 noise reduction algorithm doesn?t restrict microphone placements, but the default algorithm will operate optimally with omnidirectional microphones placed in the following configuration: ? the two microphones are facing the user?s mouth ? the microphone centers are located within 10 to 25 mm from each other as mentioned, other configurations that differ from the above guideli nes are fully supported. for example, a 15 cm distance between the two microphones will not degrade the performance as long as the microphones are both facing the user?s mouth. alternatively, a configuration with one microphone at the front and one microphone at the back will not degrade the performance either, as long as the distance between the microphones is no more than 2 cm. belasigna r262 does not require any acoustic microphone calibration procedure. when selecting microphones to be used with belasigna r262, the following guidelines should be used: ? two omni ? directional microphones with similar characteristics should be used ? the microphone sensitivity should be approximately ? 42 db (where 0 db = 1 v/pa, at 1 khz) ? the microphones are two ? terminal microphones ? the microphone power supply is either 1 v (recommended), or 2 v if it is to be provided by belasigna r262 ? the dynamic range of belasigna r262 on its analog input channels is 2.0 v peak ? to ? peak, after amplification by the default gain value of 24 db using belasigna r262?s input preamplifiers ? when higher sensitivity microphones are used, the preamp gain should be adjusted to match the 2.0 vpp input voltage swing on belasigna r262, but this will require special configuration of the rom application, as described later. as an example, using microphones with a ? 22 db sensitivity typically requires that the preamplifier gains be changed down to 12 db. ? when mems microphone are to be used, a general increase of the algorithm performance can be expected due to the improved self noise of these microphones, compared to conventional electret microphones. for applications requiring microphone configurations differing significantly from the above recommendations, contact your local on semiconductor support representative. operating modes the default application stored in the rom of belasigna r262 has four operating modes. the operating modes are summarized in table 8. table 8. operating modes summary operating mode switching description active active mode can be entered at boot time, depend- ing on the boot_sel configuration and when exiting sleep mode. active mode can also be entered via an i 2 c command from another mode. in active mode, the noise reduction algorithm is executed. while in active mode, belasigna r262 collects statistics on the input signals that can be retrieved via i 2 c. these signal statistics can be used for level calibration and other debugging. for more in- formation using active mode for calibration and debugging see the belasigna r262 communications and configuration guide. bypass bypass mode can be entered at boot time, de- pending on the boot_sel configuration. it can also be entered via an i 2 c command from another mode. in bypass mode, no signal processing is done on the audio in- puts. the inputs are passed directly to the audio outputs. while in bypass mode, belasigna r262 collects statistics on the input signals that can be retrieved via i 2 c. these signal statistics can be used for level calibration and other debugging. for more in- formation using bypass mode for calibration and debugging see the belasigna r262 communications and configuration guide. sleep sleep mode can be entered via i 2 c commands. when sleep mode is entered via i 2 c, the chip will exit sleep mode only based on activity on the i 2 c_scl pin. sleep mode will be automatically entered if belasigna r262 detects that a required external clock is no longer present. for more in- formation, see the sleep control section below. in sleep mode no signal processing is done. all analog blocks of the chip are disabled and the digital core continues to run off an internal low ? speed oscillator, thereby allowing the external clock to be disabled when the chip is asleep. this is belasigna r262?s lowest power operating mode. stand ? by stand ? by mode is an intermediate mode that is only used when exiting sleep mode by an i 2 c command. when i 2 c is used to exit sleep mode, the application will trans- ition to stand ? by mode, and will wait until the master i 2 c device issues a switch_mode command to enter another processing mode like active or bypass. if no such command is issued, be- lasigna r262 will return to sleep mode and wait for a valid wake ? up sequence.
belasigna r262 http://onsemi.com 17 boot control, hardware configuration and digital control at power ? on ? reset, belasigna r262 will normally execute the application stored in rom. during the boot process, belasigna r262 will read voltage levels on four different pins, which will determine the algorithm and hardware configuration that will be executed. all the configuration options are described later in this section; the four pins are clock_sel, boot_sel, chan_sel and alpha_sel. the boot_sel pin controls the booting methods of belasigna r262. the signal on this pin is sampled by belasigna r262 during its booting process using a low ? speed a/d converter (lsad). based on the actual voltage that the chip will read on this pin, it will automatically select a particular booting configuration, as described in table 9. table 9. boot selection options (note 4) preset voltage level boot method description 0 ? 2 0.65 ? 1.00 v external boot mode in this mode, belasigna r262 will not run the rom based applica- tion. it will start looking for an spi eeprom to bootload a custom application from. if unsuccessful, it will look for an i 2 c eeprom to bootload a custom application; and lastly, if neither of the two previ- ous operations to find an eeprom are successful, it will enter a wait loop, allowing a master i 2 c device to start downloading a cus- tom application (e.g. a baseband controller). 3 0.50 ? 0.63 v active mode talking distance selectable from near ? to far ? talk (50 cm to 500 cm) the noise reduction algorithm is running and can be configured for talking distances between 50 cm (near ? talk) and 5 m (far ? talk) 4 0.36 ? 0.49 v active mode talking distance selectable from close ? to far ? talk (5 cm to 500 cm) the noise reduction algorithm is running and can be configured for talking distances between 5 cm (close ? talk) and 5 m (far ? talk) 5 0.22 ? 0.35 v active mode talking distance selectable from close ? to near ? talk (5 cm to 100 cm) the noise reduction algorithm is running and can be configured for talking distances between 5 cm (close ? talk) and 1 m (near ? talk) 6 0.08 ? 0.21 v bypass diagnostic mode 1 khz sine wave play ? out belasigna r262 outputs a pure tone on the two output channels. this sine wave has a frequency of 1 khz and an output level of 12 db below full scale. 7 0 ? 0.07 v bypass diagnostic mode full stereo passthrough belasigna r262 simply copies the input signals to the outputs. 4. for more details on the various operating modes of belasigna r262, please consult the belasigna r262 communications and confi guration guide.
belasigna r262 http://onsemi.com 18 clocking, channels & algorithm configuration as mentioned in the boot control section, belasigna r262 is controlled by hardware configuration. just like the boot_sel signal discussed earlier, the clock_sel, chan_sel and alpha_sel pins are also sampled by belasigna r262 during its booting process using a low ? speed a/d converters (lsad). based on the actual voltage that the chip reads on these pins, it will automatically select a particular clock, output stage, channels and algorithm configuration, as described in tables 10, 11 and 12. table 10. clock configuration options preset voltage level clock frequency description 0 ? 2 0.65 ? 1.00 v 2.048 mhz a 2.048 mhz external clock is expected to be present on the ext_clk pin of belasigna r262 3 0.50 ? 0.63 v 2.4 mhz a 2.4 mhz external clock is expected to be present on the ext_clk pin of belasigna r262 4 0.36 ? 0.49 v 2.8 mhz a 2.8 mhz external clock is expected to be present on the ext_clk pin of belasigna r262 5 0.22 ? 0.35 v 3.072 mhz a 3.072 mhz external clock is expected to be present on the ext_clk pin of belasigna r262 6 0.08 ? 0.21 v 26 mhz a 26 mhz external clock is expected to be present on the ext_clk pin of belasigna r262 7 0 ? 0.07 v internal oscillator belasigna r262 runs off its internal system clock. no clock signal must be present on the ext_clk pin. in this mode the sampling frequency can fluctu- ate slightly from one device to another; see the electrical characteristics for additional details. the performance of the algorithm itself is fully guaranteed. table 11. channel configuration options preset voltage level nr outputs channel 0 channel 1 output stage configuration 0 ? 2 0.65 ? 1.00 v single start of range (as per boot_sel) n/a mono, differential 3 0.50 ? 0.63 v dual start of range (as per boot_sel) mixed output (as per boot_sel & alpha_sel) stereo, single ended 4 0.36 ? 0.49 v dual mixed output (as per boot_sel & alpha_sel) end of range (as per boot_sel) stereo, single ended 5 0.22 ? 0.35 v single mixed output (as per boot_sel & alpha_sel) n/a mono, differential 6 0.08 ? 0.21 v single mixed output (as per boot_sel & alpha_sel) algorithm disabled stereo, single ended 7 0 ? 0.07 v single algorithm disabled mixed output (as per boot_sel & alpha_sel) stereo, single ended table 12. mixer configuration options preset voltage level mixing ratio 0 ? 2 0.65 ? 1.00 v 0% (start of range) 3 0.50 ? 0.63 v 20% (between start and end of range) 4 0.36 ? 0.49 v 40% (between start and end of range) 5 0.22 ? 0.35 v 60% (between start and end of range) 6 0.08 ? 0.21 v 80% (between start and end of range) 7 0 ? 0.07 v 100% (end of range)
belasigna r262 http://onsemi.com 19 the use of a resistive divider as shown in figure 8 allows the application to select the appropriate combination of clock, output stage and algorithm mode. the lsad is using a voltage range between 0 and 1 v. the actual voltage levels that need to be guaranteed by the application circuitry are also mentioned in figure 8. the figure proposes actual resistor values to reach the eight different presets. figure 8. resistive dividers for lsad preset selection lsad pin r2 vreg r1 preset r1 r2 voltage range 0 ? 2 10 k ? 0.65 ? 1.00 v 3 75 k 100 k 0.50 ? 0.63 v 4 100 k 75 k 0.36 ? 0.49 v 5 100 k 39 k 0.22 ? 0.35 v 6 100 k 16 k 0.08 ? 0.21 v 7 ? 10 k 0 ? 0.07 v the configuration is only read by the chip at boot time. consequently, if the voltage on any of the four lsad inputs changes during operation, it will only have an impact at the next power cycle. channel swapping belasigna r262 has provisions to swap the two output channels by using an external gpio pin (swap_chan). the two output channels of belasigna r262 can be swapped whenever the digital signal on this pin transitions to low and stays low for at least 200 ms, as shown in figure 9. the actual channel swapping can occur at any time during the 200 ms low period of the signal. this control mechanism has built-in button de-bouncing and will work with either a digital signal driven high or low by a host controller, or with a control signal provided by a mechanical button or switch. figure 9. swap_chan timing diagram channel state swap_chan normal swapped normal 200 ms (min) 200 ms (min) sleep control as described in table 8, there are two methods to enter and exit from sleep mode. both of these methods are meant to be used independently, i.e. methods of putting the system into sleep mode and waking it up from sleep mode cannot be mixed in the same system design. the first method for sleep mode control is via the i 2 c interface. the switch_mode command can be used directly to switch the system into and out of sleep mode. if the switch_mode command is used to put the chip into sleep mode, only another switch_mode command or a reset will take the system out of sleep mode. when waking up by i 2 c commands, the following i 2 c operations have to be performed by the master i 2 c to ensure proper wake ? up: 1. send a nop command to wake up the i 2 c interface. this command will not be interpreted by belasigna r262, so the master will have to deal with any i 2 c errors that result. 2. send the get_status command in a while ? type loop, until a response from belasigna r262 is sent, and that confirms that the application is in standby mode. 3. send a switch_mode command to enter the desired mode (active or bypass). when the nop command is sent and the chip wakes up, the master has about one second to complete the above procedure before the chip goes back to sleep mode. this mechanism was put in place to deal with i 2 c bus traffic that would wake the chip up unintentionally (i.e. communications between the master and another slave on the i 2 c bus). the second mechanism for entering sleep mode is considered a fail safe mechanism to maintain a graceful system sh utdown in the event that the clock source suddenly disappears. in this circumstance, the chip will enter sleep mode to ensure proper shutdown. more information on this can be found in the system monitoring section.
belasigna r262 http://onsemi.com 20 i 2 c command handler the belasigna r262 rom application contains an i 2 c ? based command and control interface, allowing many aspects of the chip?s operation and hardware configuration to be controlled via i 2 c. this i 2 c interface is the recommended way to control the chip and to configure the application at run ? time. the default i 2 c address of belasigna r262 is 0x61. the i 2 c interface protocol is fully supported by the signaklara device utility (skdu) and other software tools provided by on semiconductor. for more information on the i 2 c interface, please refer to the i 2 c interface section of this document, as well as the belasigna r262 communications and configuration guide. reset belasigna r262 can be forced to execute a power ? on ? reset by pulling the nreset pin to ground for at least 100 ns. nreset is not available on the 26 ? ball wlcsp package. system monitoring the application software within belasigna r262 is equipped with a few blocks that monitor system sanity. a watchdog timer is used to ensure proper execution of the signal processing application. it is always active and is periodically acknowledged as a check that the application is still running. once the watchdog times out, a hardware system reset will occur. system sanity is also monitored by the clock detection mechanism; the chip will automatically enter sleep mode if it is in active or bypass mode and it detects that the external clock source (the signal on ext_clk) is stopped. in this case, the system will only exit sleep mode when it detects that the external clock source has been restored or a reset occurs. the power supply blocks of the system also monitor for minimum supply voltages as part of the power supervision strategy, as described in the power management section. analog blocks input stages the belasigna r262 analog audio input stage is shown in figure 10. the input stage is comprised of two individual channels. there are four configurable aspects of each channel ? input multiplexing, preamplifier gain, filtering and line out. the input multiplexing allows one input to be selected from any of the four possible inputs and then routed to the input of the preamplifier. each preamplifier can be configured for bypass or gain values of 12 to 30 db in 3 db steps. the filters can be configured as well; the dc removal high ? pass filter can be bypassed, or set to a cut ? off frequency of 5 hz, 10 hz or 20 hz (default). the low ? pass filter can be either enabled with a 20 khz cut ? off frequency (default), or bypassed. the lineout selection allows the preamplifier outputs to be routed back out via the auxiliary audio input pins. note that the ai1/lout1 pin is not available on the 26 ? ball wlcsp package option. two analog ? to ? digital converters then convert the analog signals into the digital domain. the adcs are running at a sampling rate of 21.3 khz in active mode and 16 khz in bypass mode. the sampling rate can potentially be changed using the i 2 c interface. changing the sampling rate in active mode will cause the noise cancellation algorithm to stop operating properly, so this should not be done; however, the sampling rate in bypass mode could be changed to other values. contact your local technical support for more information. input signal amplitudes can also be adjusted in the digital domain; digital gain for both converted signals can be adjusted by using i 2 c commands. the rom ? based application pre ? configures all these parameters in the input stage such that the algorithm operates properly. these parameters can be changed using the i 2 c interface, but careful design consideration should be taken when doing so, as this could alter the performance of the algorithm. the ai3 pin is multiplexed with the microphone power supply (vmic). the default mode for the microphone bias is to be used as a 2 v power supply. consequently, any application that plans to use the ai3 input pin or the lout0 functionality has to change the vmic setting to high ? impedance mode, such as the pin can be properly used as an analog input or a line ? out.
belasigna r262 http://onsemi.com 21 figure 10. input stage adc0 to iop adc1 line out decimation filter mic0 ai1/lout1 line out to iop digital analog input stage channel 0 m u x mic2 ai3/vmic/lout0 m u x input stage channel 1 decimation filter pa0 lpf0 pa1 lpf1 output stage at all times, the application will produce two output channels. the content of each channel is determined by the hardware configuration. the amplitude of both output channels can be controlled by i 2 c commands, independently from the actual output stage configuration that was selected. a first parameter controls gain in 6 db steps. a second parameter is a variable for fine gain adjustment. with these two parameters, a great level of flexibility is achieved to match the output level requirements of the target device, independently for each of the two output channels. the application has initialized these parameters for proper operation of the algorithm and correct output so careful design consideration should be taken when modifying these parameters. the belasigna r262 output stage is shown in figure 11. the output stage processes two channels although, depending on the configuration, one or both of the output signals are available on the output pins. there are four options for audio outputs from belasigna r262 ? a digital microphone (dmic) interface, a low ? impedance output driver, a stereo single ? ended analog output or a mono differential analog output. all outputs are generated from a sigma ? delta modulator which produces a pulse density modulated (pdm) output signal and then provides it to the appropriate output system, based on the system configuration. figure 11. output stage interpolation filter output driver 0 a_out0 a_out1 combiner dmic_out from application channel 0 dac0 dac1 from application channel 1 digital analog output stage channel 0 output modulator interpolation filter output stage channel 1 output modulator m u x inversion delay , inversion and muxing oa0 lpf oa1 lpf the digital microphone interface provides the pdm signals directly on a pin (dmic_out), for interfacing with the dmic input of external systems. when using this interface, the ext_clk input to belasigna r262 must be given a dmic_clk signal and the system clocking must be set up such that proper synchronization can happen between the incoming dmic_clk and the output data produced by belasigna r262 on its dmic_out pin. various dmic_clk frequencies are supported through hardware configuration on the clock_sel pin, as discussed earlier. other frequencies can also be supported under certain conditions; see the clocking section of this document for
belasigna r262 http://onsemi.com 22 more information on the supported dmic clock frequencies. the dmic output can be configured to carry a mono or stereo signal. in fact both left and right signals can be configured to either contain output stage channel 0 or output stage channel 1. also, both left and right can be configured to be muted independently (driving a ?0? all the time). figure 12 shows the timing of the dmic output data relative to the incoming dmic_clk signal. see table 2 for electrical specifications of the timing parameters. figure 12. dmic timing diagram dmic_clk dmic_data left data 0 right data 2 dmic_ hold dmic_ hold dmic_ setup dmic_ setup right data 0 left data 1 right data 1 the application pre ? configures the dmic interface based on the chan_sel pin; when in a stereo configuration, it always outputs a stereo signal with channel 0 as the right signal, and channel 1 as the left signal. when in a mono configuration, both the right and left signals will contain the data processed on channel 0, unless the swap_chan pin was used to toggle the channels, in which case the dmic output would see the channel 1 output on both left and right signals. when the dmic interface is not required, the analog outputs can be used for interfacing at line ? level or other signal levels, e.g. microphone levels for an external system such as an analog baseband chipset which expects low ? level signals. there are two configurable aspects of the analog output stage ? the selection of stereo (two single ? ended outputs) or mono (one differential output) and the output attenuation. when a stereo single ? ended option is selected, each channel is filtered to generate an analog signal which is then scaled by a configurable output attenuator (oa in figure 12). in mono differential mode, channel 1 is replaced by an inverted version of channel 0 such that the two output pins contain a differential signal for channel 0. in this latter case, both output attenuators are used, so it is mandatory to ensure that they have the same attenuation settings. the default attenuation value is 0 db for both channels. this can be configured using i 2 c commands. the 26 ? ball wlcsp package option doesn?t provide access to a_out0. consequently, only a_out1 is available as an analog output. when using this package, careful design consideration must be taken to ensure that the desired signal is available on channel 1, i.e. on the a_out1 pin. a third output stage option is available on belasigna r262; using the class ? d output driver which can drive an output transducer without the need for a separate power amplifier. the output driver can also be configured for single ended stereo or differential mono through the same i 2 c commands as described for the analog outputs. the output driver is disabled by the default application in rom. for optimal audio performance it is important to note that the vbatrcvr power supply must be connected differently, depending on whether the output driver or the analog outputs are being used: ? when using the analog outputs, vbatrcvr must be connected to vdda on the application pcb ? when using the output driver, vbatrcvr must be connected to vbat on the application pcb and must be decoupled with an external capacitor when interfacing belasigna r262 with other processors like codecs or baseband chipsets, it is not recommended to use the class ? d output driver, but rather the analog outputs. clock generation circuitry belasigna r262 is equipped with a fully configurable and flexible clocking system, which allows for many clocking configurations for various use cases. computing applications typically require the use of a dmic interface, which imposes constraints on the belasigna r262 clocking system, such as it provides full synchronization between an incoming dmic clock and the dmic data that the chip will produce. the clock frequencies that these systems usually operate with are in the range of 2.048 to 3.072 mhz. mobile phone applications would typically use much higher clock frequencies; historically, baseband systems have been using 13 mhz or 26 mhz, or even 19.2 mhz or 38.4 mhz. to support such a wide variety of clocking scenarios, belasigna r262 has a phase locked loop (pll) integrated as one of the components of its clock generation circuitry. clock frequencies can be selected using the clock_sel pin, as discussed previously. belasigna r262 can also operate on its internal rc oscillator, offering the same
belasigna r262 http://onsemi.com 23 performance, with the slight drawback that the sampling frequency will vary from device to device due to process variation affecting the rc oscillation frequency. when belasigna r262 is used with its analog outputs, this has no affect on performance and can be used safely. when synchronization with an external system is required, such as a dmic codec, it is not possible to use the internal oscillator. for more information on the configuration of this clocking architecture, refer to the belasigna r262 communications and configuration guide. power supply unit belasigna r262 uses multiple power supplies as can be seen on the simplified representation of the power supply unit in figure 13. vdda vreg vbat vreg regulator cap0 cap1 charge pump vssa vddd regulator bandgaps & regulators vddd vssd por & power supervision vmic m u x vddo vbatrcvr figure 13. power supply structure 2 v 1 v 1.8 v digital and analog sections of the chip have their own power supplies to allow exceptional audio quality. several band gap reference circuits and voltage regulators are used to separate the power supplies to the various blocks that compose the belasigna r262 architecture. table 13 provides a short description of all the power supply pins of belasigna r262. table 13. power supply voltages voltage abbreviation description battery supply voltage vbat the primary voltage supplied to belasigna r262 is vbat. it is typically in the range 1.8 v ? 3.3 v. belasigna r262 has internal voltage regulators that allow the application pcb to avoid the use of external voltage regulators. output driver supply voltage vbatrcvr if powered independently and the output driver is to be used, vbatrcvr must be connected to vbat on the application pcb. alternatively, if the analog outputs are used, vbatrcvr should be connected to vdda. a decoupling capacitor is only required when the output driver is being used. internal digital supply voltage vddd the internal digital supply voltage is used as the supply voltage for all internal digital components, including being used as the interface voltage at the internal side of the level translation circuitry attached to all of the digital pins. vddd is provided as an output pad, where a decoupling capacit- or to ground must be placed to filter power supply noise. external i/o supply voltage vddo vddo is an externally provided power source. it is used by belasigna r262 as the external side of the level translation circuitry attached to all of the digital pins. communication with external devices on digital pins will happen at the level defined on this pin. regulated supply voltage vreg vreg is a 1 v reference to the analog circuitry. it is available externally to allow for additional noise filtering of the regulated voltages within the system. vreg can also be used as a micro- phone power supply, when the vmic pin cannot be used. analog supply voltage vdda vdda is a 2 v reference voltage generated from the internal charge pump. it is a reference to the analog circuitry. it is available externally to allow for additional noise filtering of the regulated voltages within the system. the internal charge pump uses an external capacitor that is periodic- ally refreshed to maintain the 2 v supply. vdda can also be used as a microphone power supply, when the vmic pin cannot be used. microphone bias voltage vmic vmic is a configurable microphone bias voltage. vmic can be configured by the application to provide a 1 v or 2 v power supply to the microphones. it can also be grounded or put to high ? z mode to save power when the microphones don?t have to be used. the rom ? based application configures vmic to provide 2 v to the microphones when they are in use, and high ? z when the system is in sleep mode.
belasigna r262 http://onsemi.com 24 power management strategy & battery monitoring belasigna r262 has a built ? in power management unit that guarantees valid system operation under any voltage supply condition to prevent any unexpected audio output as the result of any supply irregularity. the unit constantly monitors the power supply and shuts down all functional units (including all units in the audio path) when the power supply voltage goes below a level at which point valid operation can no longer be guaranteed. the power management unit on belasigna r262 includes power ? on ? reset (por) functionality as well as power supervisory circuitry, as shown in figure 13. these two components work together to ensure proper device operation under all supply conditions. the por sequence is designed to ensure proper system behavior during start ? up and proper system configuration after start ? up. at the start of the por sequence, the audio output is disabled and all configuration and control registers are asynchronously reset to their default values. the power supervisory circuitry monitors the supply voltage (vbat). this circuit is used to start the system when vbat reaches a safe startup voltage, and to reset the system when it drops below a relevant voltage threshold. the relevant parameters are shown in table 14. table 14. power management parameters parameters voltage level vbat startup 1.65 v 80 mv vbat shutdown 1.6 v 50 mv the por sequence consists of two phases: voltage supply stabilization and boot rom initialization. during the voltage supply stabilization phase, the following steps are performed: 1. the internal regulators are enabled and allowed to stabilize 2. the internal charge pump is enabled and allowed to stabilize 3. sysclk is connected to all of the system components (free ? running pll output) 4. the system runs the rom application at step 1, once the supply voltage rises above the startup voltage and remains there for more than 5 ms, a signal will enable the charge pump. at step 2, another 5 ms delay is implemented to allow the charge pump to stabilize before toggling the por signal, and thus enabling the digital core. if the supply is consistent, the internal system voltage will then remain at a fixed nominal voltage. if a spike occurs that causes the voltage to drop below the shutdown internal system voltage, the system will shut down. if the voltage rises again above the startup voltage and remains there for the required time, a por sequence will occur again. once the rom application is running, more system monitoring is performed by the application; typically, the software will permanently monitor the presence of an external clock, and take the appropriate actions whenever it disappears. see the system monitoring section for more information. digital communication interfaces debug port (uart) belasigna r262 has an rs232 ? based uart that can be used to interface the chip from on semiconductor?s communication tools. the debug port cannot be used for customer applications. belasigna r262 can only be configured using the i 2 c interface. see the i 2 c interface section for information on how communication tools can interface with belasigna r262. general ? purpose input output (gpio) belasigna r262 has five gpio pins which are all used with spec ific functionalities. the five signals are spi_clk/ clock_sel, spi_cs/boot_sel, spi_sero/ chan_sel, spi_seri/alpha_sel and sw ap_chan. swap_chan is used as a gpio, consequently, it has an internal pull up resistor. when used as lsads (clock_sel, boot_sel, chan_sel and alpha_sel), the pull ups are disabled. if left floating in lsad mode, the pins have a weak pull down to ground. see the booting control, output and channel control and algorithm control sections earlier in this document for details on the behavior of these gpio and lsad pins. serial peripheral interface (spi) port an spi port is available on belasigna r262 for applications such as communication with non ? volatile memory (eeprom). the i/o levels on this port are defined by the voltage on the vddo pin. the spi port operates in master mode only, which supports communications with slave spi devices. the four signals needed by the spi port are multiplexed with other functions on belasigna r262 (gpios, lsads). the use of the spi port requires careful design consideration with regards to the use of these other functions. i 2 c interface the i 2 c interface is an industry standard interface that can be used for high speed transmission of data between belasigna r262 and an external device. the interface operates at speeds up to 400 kbit/sec. in product development mode, the i 2 c interface is used for application debugging purposes, communicating with the belasigna r262 development tools, also known as signaklara development utility (skdu). the interface always operates in slave mode and the slave address is 0x61. a comprehensive command interface can be used with the skdu and other tools provided by on semiconductor. it will of fer a variety of support functions grouped in different categories like general system control (system reset, status information), application control (switching between operating modes, enabling or disabling the algorithm),
belasigna r262 http://onsemi.com 25 hardware setup (for custom configuration of the various hardware units like clocking, input/output stages), algorithm setup (amplitude management, tuning selection) and finally the low level i 2 c protocol is also supported. the i 2 c interface can also be used to communicate with a slave i 2 c eeprom. using an i 2 c eeprom instead of an spi eeprom provides better flexibility as it avoids potential conflicts between gpio/lsad pins and the spi pins. more details on this command interface can be found in the belasigna r262 communications and configuration guide. interfaces unused by the rom ? based application belasigna r262 also contains hardware provisions for a high speed pcm interface, as well as a high speed uart. these two interfaces are not used by the rom ? based application, hence cannot be used by default. custom applications developed by on semiconductor could enable the use of these interfaces, should this be required. long term storage conditions on semiconductor specifies a 24 ? month maximum storage time for wlcsp devices in pocket tapes and conditioned in dry bags, as stated in table 15 below and defined in on semiconductor?s finished goods packing and long term storage procedures. table 15. long term storage conditions storage condition maximum storage time remarks temperature 18 ? 28 c, humidity 30 ? 65%rh 24 months after die singulation/sawing date maximum 12 months storage at condition 18 ? 28 c, 30 ? 65%rh. after- wards storage in vacuum moisture bag with desiccant and humidity card. storage in nitrogen cabinet allowed. re ? flow information the re ? flow profile depends on the equipment that is used for the re ? flow and the assembly that is being re ? flowed. careful design consideration must be taken not to expose the packages to temperatures above the rated features. the wlcsp package is tested to perform reliably up to 3x reflow passes at the maximum reflow peak temperature of 260 c. use table 16 from the jedec standard 22 ? a113d and j ? std ? 020d as a guideline but note that actual profiles should be developed by customers based on specific process needs and board designs. table 16. re ? flow information profile feature pb ? free assembly preheat & soak temperature minimum (tsmin) temperature maximum (tsmax) time (tsmin to tsmac) (ts) 150 c 200 c 60 ? 120 seconds average ramp ? up rate (tsmax to tp) 3 c/second maximum liquidous temperature and time temperature (tl) time (tl) 217 c 60 ? 150 seconds peak temperature (tp) 260 +0/ ? 5 c time within 5 c of actual peak temperature 20 ? 40 seconds ramp ? down rate (tp to tsmax) 6 c/second maximum time 25 c to peak temperature 8 minutes maximum device weight belasigna r262 has an average weight of 10.84 mg. miscellaneous chip identification chip identification information can be retrieved by using the communications accelerator adaptor (caa) along with protocol software provided by on semiconductor. for belasigna r262, the key identifier components and values are as follows: chip family chip version 0x02 (sk2) 0x3021
belasigna r262 http://onsemi.com 26 package dimensions wlcsp30, 2.233x2.388 case 567ct ? 01 issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.84 millimeters a1 d 2.388 bsc e b 0.24 0.29 ea 0.252 bsc 1.00 d e a b pin a1 reference ea a 0.05 b c 0.03 c 0.05 c 30x b 123 a b c 0.10 c a a1 a2 c 0.17 0.23 2.233 bsc eb 0.310 bsc pitch 0.25 30x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.504 0.310 0.10 c 2x top view side view bottom view note 3 eb a2 0.72 ref recommended a1 package outline 456 789 d e f g
belasigna r262 http://onsemi.com 27 package dimensions wlcsp26, 2.388x2.233 case 567cy ? 01 issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max 0.84 millimeters a1 d 2.388 bsc e b 0.24 0.29 ed 0.252 bsc 1.00 d e a b pin a1 reference ed a 0.05 b c 0.03 c 0.05 c 26x b 123 a b c 0.10 c a a1 a2 c 0.17 0.23 2.233 bsc ee 0.310 bsc pitch 0.25 26x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.504 0.31 0.10 c 2x top view side view bottom view note 3 ee a2 0.72 ref recommended a1 package outline 456 789 d e f g
belasigna r262 http://onsemi.com 28 assembly / design notes for pcb manufacture with belasigna r262, on semiconductor recommends solder ? on ? pad (sop) surface finish. with sop, the solder mask opening should be non ? solder mask ? defined (nsmd) and copper pad geometry will be dictated by the pcb vendor?s design requirements. alternative surface finishes are enig and osp; volume of screened solder paste (#5) should be less than 0.0008 mm 3 . if no pre ? screening of solder paste is used, then the following conditions must be met: 1. the solder mask opening should be >0.3 mm in diameter 2. the copper pad should have a diameter of 0.25 mm 3. solder mask thickness should be less than 1 mil thick above the copper surface for pcb manufacture with the 26 ? ball wlcsp version of belasigna r262, any vias that might be placed below the wlcsp should all be covered in soldermask. the assembly process can use underfill under the wlcsp; it will provide another physical dielectric barrier, and will also enhance long term reliability over temperature and physical shock. on semiconductor can provide belasigna r262 mounting footprint guidelines to assist your pcb design upon request. table 17. ordering information device marking package shipping ? BR262W30A103E1G br262w30 wlcsp30 2500 / tape & reel br262w26a103e1g br262w26 wlcsp26 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 br262/d belasigna is a registered trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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